(1) Field of the Invention
The present invention relates to semiconductor integrated Circuit processing, and more particularly, to etching processes compatible with ULSI technology.
(2) Description of Prior Art
The salicide (self-aligned silicide) process is an integral part of ULSI technology. In this process a metallic layer, titanium or cobalt, is deposited over the entire wafer and heated in a nitrogen environment, so that silicide is formed in regions where the metal is in contact with silicon. These could be exposed source and drain regions and bare surfaces of polysilicon gates and lines. The unreacted metal is removed by an etchant that does not attack silicide, silicon or oxide. Thus a silicide layer can be patterned without a masking step.
A process for patterning local interconnections based on the salicide process is described in U.S. Pat. No. 4,657,628 to Holloway et. al. Using titanium as the metal, a layer of titanium silicide is formed where silicon was left exposed. Instead of removing the unreacted metal, a hardmask is deposited and patterned over the titanium. A conductive titanium nitride layer formed subsequently will be patterned according to the hardmask. Alternatively, the patterning step could precede formation of the titanium nitride.
In U.S. Pat. No. 555,431,770 to Lee et, al. a method of forming features, gates or lines for example, with sublithographic dimensions is disclosed. A hardmask is patterned over layers of oxide or polysilicon, for example. The dimension of the hardmask is reduced by an isotropic etch. An ensuing anisotropic etch will produce a feature of smaller dimension than the original mask.
A planarization technique involving a buffer layer is disclosed in U.S. Pat. No. 5,372,673 to Stager et. al. A buffer layer is applied so that its surface is more planer than the surface it covers. By appropriately monitoring and altering the etch process, the surface of the original layer can be made relatively planar.
The present invention is particularly relevant to situations in which a hardmask is used in patterning ultra narrow polysilicon, or amorphous silicon, lines. Since the hardmask is not compatible with the salicide process, it must be removed. In removing the hardmask it is important to insure that other regions; such as, the silicon substrate, the polysilicon gate sidewall and the shallow trench insulation; are not damaged. Such damage would impact the yield and reliability of the product.
The conventional approach involves a seven step process. After the polysilicon gate patterning step there exist regions of silicon, polysilicon gate covered with a hardmask and shallow trench insulation (assuming this to be the isolation scheme, for example). An overall buffer layer is deposited and, in the third step, etched back to expose the hardmask. Following removal of the hardmask, using a selective removal method, the remaining buffer material is removed by an O2 plasma asher followed by a wet cleaning step, such as an RCA bath. Finally, the seventh step involves salicide formation.
FIGS. 2A-2F schematically shows the salicide process flow when the conventional approach is used. After patterning the polysilicon gate, FIG. 2A, a buffer layer, photoresist for example, is deposited, FIG. 2B, as in the process flow according to the present invention. A partial ashing is then performed to expose the hardmask, FIG. 2C. The fourth step is hardmask removal, FIG. 2D. This is accomplished in various ways for the different hardmasks. Generally, a different tool is required than that used to partially remove the buffer layer. Dry or wet etching or chemical and mechanical polishing are removal methods conventionally used. Different methods are used for the common hardmask materials; SiON, Si3N4 and various forms of SiO2; since not all methods work equally well for the different hardmasks. Damage is likely in any of these methods. Next, the remaining buffer layer is removed, commonly by O2 asher, and the sixth step is a Caro's cleaning step to prepare the wafer for salicide formation, the seventh step, FIG. 2F.